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Wang Yanrong, Yang Hong, Xu Hao, Luo Weichun, Qi Luwei, Zhang Shuxiang, Wang Wenwu, Yan Jiang, Zhu Huilong, Zhao Chao, Chen Dapeng, Ye Tianchun. Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process. Chinese Physics B, 2017, 26(8): 087304  
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Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process
Wang Yanrong1, 2, 3, Yang Hong1, 3, Xu Hao1, 3, Luo Weichun1, 3, Qi Luwei1, 3, Zhang Shuxiang1, 3, Wang Wenwu1, 3, †, Yan Jiang2, Zhu Huilong1, 3, Zhao Chao1, 3, Chen Dapeng1, 3, Ye Tianchun1, 3
Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of MicroElectronics, Chinese Academy of Sciences, Beijing 100029, China
North China University of Technology, Beijing 100144, China
University of Chinese Academy of Sciences, Beijing 100049, China

 

† Corresponding author. E-mail: wangwenwu@ime.ac.cn

Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA016501) and the National Natural Science Foundation of China (Grant No. 61306129).

Abstract

In the process of high-k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.

PACS: 73.40.Qv;77.55.D-;85.30.Tv
Keyword:high-k/metal gate;multi deposition multi annealing;stress-induced leakage current;post deposition annealing
1. Introduction

The continuous scaling of device dimension has aggravated the problem of leakage current and gate oxide reliability. HfO2 as a promising high-k material has replaced the traditional SiO2 in the fabrication of nanometer devices;[1,2] it is widely used in the 22-nm node metal–oxide–semiconductor field-effect transistor (MOSFET).[3] The introduction of a high-k/metal gate (HK/MG) into manufacturing has enabled the continuance of device scaling. However, the multi-layer structure also brings reliability problems[4,5] such as stress-induced leakage current (SILC)[6,7] especially in the gate last process. One of the reasons that leads to a severe reliability problem is the small thermal budget. The small thermal budget leads to more traps in the dielectric and a larger gate leakage current. Therefore, the annealing process, namely, post deposition annealing (PDA) would be a beneficial method to improve the reliability of the metal–oxide–semiconductor (MOS) devices.[8] Generally, simple annealing is applied in the manufacturing process. It is discovered that this cannot optimize the reliability problem. Then a new annealing method is proposed.[9,10] But more detailed and systematic analysis about the influence of MDMA on the reliability characteristic, including SILC, is absent. In this paper, the annealing time effects on the SILC characteristic are studied.

2. Experiment

In this experiment, (100) n-type Si wafers with resistivity of 2 4 Ω are prepared by diluted buffered oxide etch solution (NH4F:HF D 7:1). The SiO2/HfO2/TiN gate stack is fabricated with the Si wafer by a gate-last process. The interface layer (IL) is grown using the O-zone method, and the 28 cycles of HfO2 films are deposited by atomic layer deposition (ALD) using the multi-deposition multi-annealing (MDMA) technique. Four samples with different deposition and annealing (D & A) cycles are prepared. The D & A cycle(s) of samples A, B, C, and D are 1, 2, 4, and 7 respectively as shown in Table 1; for each D & A cycle of these samples, the film is annealed at 450 °C in an N2/O2 (N2:O2 = 10:1) ambient for 15 s. The stacked metal gate consists of 2-nm TiN, 2-nm Ti, TiN, and 75 nm⋅W.

Table 1.

MDMA details of these four samples.

.

The TiN as a barrier layer is deposited by atomic layer deposition (ALD). In this process the cycles of HfO2 are kept the same for these four samples. Then Ti is formed by physical vapor deposition (PVD) followed by ALD W as the gate electrode. After preparation of the devices, the capacitance (C) and leakage current are measured with a Keithly 4200-SCS semiconductor parameter analyzer. Then the reliability characteristics are evaluated with an Agilent 4156C. In the SILC test, MOS capacitors are stressed in the accumulation area for constant voltage stress (CVS). The areas under test are all 100 μm2.

3. Results and discussion
3.1. Basic electrical characterization

Generally, the HfO2 film is treated with one-time PDA, and its C–V and I–V characteristics are shown in Fig. 1 comparing with other multi-annealing samples.

Fig. 1. (color online) (a) The C–V curve of p-MOSCAPs. (b) The – characteristics of p-MOSCAPs.

The EOTs of the four samples are shown in Fig. 2(a). The EOT is extracted from the C–V curves measured at 1 MHz using the UC-Berkley quantum-mechanical C–V simulator. It demonstrates that increasing the PDA times properly can improve the electrical characteristics of the devices including the EOT and gate leakage current. But when the PDA times increase to 7, the EOT of the device increases which was not expected. Then it is deduced that to improve the electrical properties of the devices of sub-1nm EOT, the MDMA technique can be applied and the D & A cycles must be chosen properly.

Fig. 2. (color online) (a) EOT versus PDA times. (b) Gate leakage current @ V versus PDA time.
3.2. Physical characterization

The TEM results are shown in Fig. 3.[11] Generally the physical thicknesses of the interface layer (IL) and the high-k layer are consistent with the EOT of each sample except sample 2. The physical thickness of sample 1 is bigger than that of sample 2, while the leakage of sample 1 is larger than that of sample 2. Therefore, it is deduced that the quality of the high-k layer of sample 2 is better than that of sample 1. The content of oxygen in HfO2 of each sample is shown in Fig. 4. The atom number percent O/Hf of sample 2 is closer to the ideal number 2 than sample 1. This is consistent with the above deduction.

Fig. 3. (color online) TEM pictures show the EOT of these four samples: (a) PDA 15-s 1 time. (b) PDA 15-s 2 times. (c) PDA 15-s 4 times. (d) PDA 15-s 7 times.
Fig. 4. (color online) EDX spectrum of HK layers of the samples with (a) PDA 15-s 1 time: oxygen content 59.41%, (b) PDA 15-s 2 times: oxygen content 64.67%, (c) PDA 15 s 4 times: oxygen content 74.46%, and (d) PDA 15-s 7 times: oxygen content 77.19%.
3.3. Stress-induced leakage current

The results of the electric characteristics test have shown that proper PDA cycles can contribute to the improvement of the basic performance of the device. To further verify that this MDMA technique can be applied in the manufacturing of the devices, the reliability properties SILC of the devices are studied. The sense-stress-sense method is used. The constant voltage is applied to each sample at a certain time. After the stress, the – relationship of the device is recorded. The stress voltage in our experiment is 2 V. The results of the SILC test of the four samples are shown in Fig. 5. The trap generation rates are sensed at 1.0 V as shown in Fig. 6.

Fig. 5. (color online) The SILC characteristics of the four samples.
Fig. 6. (color online) The trap generation rates at the sense voltage (SILC peak) of the four samples.

The increase of PDA times can decrease the generation rate of the devices. It is reported that the SILC is induced by an increase in the amount of shallow defect levels.[12] The two most likely intrinsic defects in terms of their formation energies are the oxygen vacancy and oxygen interstitial.[13–15] The energy of the oxygen interstitial is deeper as calculated by K. Xiong,[15] therefore, the most likely kind of defect that leads to SILC is the oxygen vacancy. The EDX spectra results as shown in Fig. 4 indicate that the atom number percent O/Hf of sample 1 and sample 2 is less than 2, while the atom number percent O/Hf of sample 3 and sample 4 is more than 2. This means that the type of oxygen vacancy of these four samples are different. It is conjectured that the oxygen vacancy of sample1 and 2 may be V+ and that the oxygen vacancy of samples 3 and 4 may be V−.

4. Conclusion

The MDMA technique applied in the HKMG gate-last process is certified to reduce the gate leakage and affect the SILC characteristic of the devices. The increase of the PDA time(s) from 1 to 2 can decrease the defect in the HK layer. However increasing the PDA times to 4 and 7 may introduce too much oxygen which is to the disadvantage of the reliability characteristics of the devices. In order to optimize the performance of the devices, proper PDA times should be chosen.

Reference
[1] Auth C Cappellani A Chun J S et al. 2008 Symposium on VLSI Technology (VLSIT) June, 17-19, 2008 Honolulu, HI, USA 128 10.1109/VLSIT.2008.4588589
[2] Auth C Allen C Blattner A et al. 2012 Symposium on VLSI Technology June, 12–14, 2012 Honolulu, HI 131 10.1109/VLSIT.2012.6242496
[3] Matsuki T Toni K Maeda T Syoji H Kiyono K Akasaka Y Hayashi K Kasai N Arikado T 2004 IEEE International Conference on Microelectronic Test Structures March, 22–25, 2004 Awaji Yumebutai, Japan 105 10.1109/ICMTS.2004.1309310
[4] Ribes G Mitard J Denais M Bruyere S Monsieur F Parthasarathy C Vincent E Ghibaudo G 2005 IEEE Trans. Dev. Mater. Reliab. 5 5
[5] O'Connor R Pantisano L Degraeve R et al. 2008 International Reliability Physics Symposium (IRPS) April 27–May 1, 2008 Phoenix, AZ, USA 324 10.1109/RELPHY.2008.4558906
[6] Hu S G Hao Y Ma X H Cao Y R Chen C Wu X F 2009 Chin. Phys. 18 5479
[7] Wang Y G Xu M Z Tan C H Zhang J F Duan X R 2005 Chin. Phys. 14 1886
[8] Cartier E Hopstaken M Copel M 2009 Appl. Phys. Lett. 95 042901
[9] Nabatame T Iwamoto K Ota H Tominaga K Hisamatsu H Yasuda T Yamamoto K Mizubayashi W Morita Y Yasuda N Ohno M Horikawa T Toriumi A 2003 IEEE VLSI Symp. June, 10-12, 2003 Yoto, Japan 25 10.1109/VLSIT.2003.1221068
[10] Wu L Yew K S Ang D S Liu WJ Le T T Duan T L Hou C H Yu X F Lee D Y Hsu K Y Xu J Tao H J Cao M Yu H Y 2010 IEEE International Electron Devices Meeting (IEDM) December, 6–8, 2012 YSan Francisco, CA, USA 273 10.1109/IEDM.2010.5703343
[11] Zhang S X Yang H Tang B Tang Z Y Xu Y F Xu J Yan J 2014 J. Semicond. 35 106001
[12] Öttking R Kupke S Nadimi1 E Leitsmann R Lazarevic F Plänitz P Roll G Slesazeck S Trentzsch M Mikolajick T 2014 Phys. Status Solidi 212 547
[13] Foster A S Gejo FL Shluger A L Nieminen R N 2002 Phys. Rev. 65 174117
[14] Foster A S Sulimov V B Gejo F L Shluger A L Nieminen R N 2001 Phys. Rev. 64 224108
[15] Xiong K Robertson J Gibson M C Clark S J 2005 Appl. Phys. Lett. 87 183505